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february 2010 doc id 16498 rev 1 1/33 33 l6728d single-phase pwm controller with power good features flexible power supply from 5 v to 12 v power conversion input as low as 1.5 v 0.8 v internal reference 0.8% output voltage accuracy high-current integrated drivers power good output sensorless and programmable ocp across low-side r ds(on) ov / uv protection vsen disconnection protection oscillator internally fixed at 300 khz lsless to manage pre-bias startup adjustable output voltage disable function internal soft-start dfn10 package applications memory and termination supply subsystem power supply (mch, ioch, pci, etc.) cpu and dsp power supply distributed power supply general dc-dc converters description l6728d is a single-phase step-down controller with integrated high-current drivers that provides complete control logic and protection to simplify the design of general dc-dc converters by using a compact dfn10 package. device flexibility allows the management of conversions with power input (v in ) as low as 1.5 v, and device supply voltage ranging from 5 v to 12 v. the l6728d provides a simple control loop with voltage mode ea. the integrated 0.8 v reference allows output voltages regulation with 0.8% accuracy over line and temperature variations. the oscillator is internally fixed to 300 khz. the l6728d provides programmable dual level overcurrent protection, as well as overvoltage and undervoltage protection. current information is monitored across the low-side mosfet r ds(on) , eliminating the need for expensive and space- consuming sense resistors. a pgood output easily provides real-time information on output voltage status, through the vsen dedicated output monitor. dfn10 table 1. device summary order codes package packaging l6728d dfn10 tube L6728DTR tape and reel www.st.com
contents l6728d 2/33 doc id 16498 rev 1 contents 1 typical application cir cuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description and c onnection diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.1 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 low-side-less startup (lsless) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.1 overcurrent threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 output voltage setting and protec tions . . . . . . . . . . . . . . . . . . . . . . . . 15 10 application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10.1 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10.2 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.1 inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.2 output capacitor(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.3 input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
l6728d contents doc id 16498 rev 1 3/33 12 20 a demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12.1 board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1.1 power input (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1.2 output (vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1.3 signal input (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1.4 test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1.5 board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13 5 a demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13.1 board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.1.1 power input (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.1.2 output (vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.1.3 signal input (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.1.4 test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.1.5 board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
typical application circuit and block diagram l6728d 4/33 doc id 16498 rev 1 1 typical application circuit and block diagram 1.1 application circuit figure 1. typical application circuit of the l6728d 1.2 block diagram figure 2. block diagram of the l6728d 1 3 2 boot ugate phase lgate / oc 4 hs ls v in = 1.5v to 12v l c out vout load c hf c bulk c dec fb 8 r fb comp / dis 7 r f c f c p gnd vcc v cc = 5v to 12v 6 5 l6728a reference schematic l6728a r ocset pgood r pg pgood vsen 10 9 r os r os r fb l6728d l6728d vcc boot lgate / oc fb ugate comp / di s gnd adaptive anti cro ss conduction h s l s vcc error amplifier + - 0. 8 v 3 00 khz o s cillator pwm pha s e control logic & protection s v octh oc l672 8 a i oc s et pgood v s en v out monitor clock l6728d
l6728d pin description and connection diagram doc id 16498 rev 1 5/33 2 pin description and connection diagram 2.1 pin descriptions figure 3. pin connection (top view) l6728d table 2. pins description pin n name function 1boot hs driver supply. connect through a capacitor (100 nf) to the floating node (ls-drain) pin and provide necessary bootstrap diode from vcc. 2 phase hs driver return path, current-reading and ad aptive-dead-time monitor. connect to the ls drain to sense r ds(on) drop to measure the output current. this pin is also used by the adaptive-dead-time control circuitry to monitor when hs mosfet is off. 3 ugate hs driver output. connect directly to hs mosfet gate. 4 lgate / oc lgate : ls driver output. connect di rectly to ls mosfet gate. oc : overcurrent threshold set. during a short period of time followin g vcc rising over the uvlo threshold, a 10 a current is sourced from this pin. connect to gnd with an r ocset resistor greater than 5 k to program the oc threshold. the resulting voltage at this pin is sampled and held internally as the oc set point. the maximum programmable oc threshold is 0.55 v. a voltage greater than 0.6 v activates an internal clamp and causes the oc threshold to be set at the maximum value. 5gnd all internal references, logic and drivers are connected to this pin. connect to the pcb ground plane. 6vcc device and driver power supply. operating range from 5 v to 12 v. filter with at least 1 f mlcc to gnd. 7 comp / dis comp: error amplifier output. connect with an r f - c f // c p to fb to compensate the device control loop. dis: the device can be disabled by pushing this pin lower than 0.75 v (typ). by setting the pin free, the device is enabled again. 8fb error amplifier inverting input. connect with a resistor r fb to the output regulated voltage. an output resistor divider may be used to regulate voltages higher than the reference. 9 vsen regulated voltage sense pin for ovp and uvp pr otection and pgood. connect to the output regulated voltage, or to the output resistor di vider if the regulated voltage is higher than the reference. 10 pgood open drain output set free after ss has finish ed and pulled low when vsen is outside the relative window. pull up to a voltage equal or lower than vcc. if not used it can be left floating.
thermal data l6728d 6/33 doc id 16498 rev 1 3 thermal data table 3. thermal data symbol parameter value unit r th(ja) thermal resistance junction-to-ambient (device soldered on 2s2p, 67 mm x 69 mm board) 45 c/w r th(jc) thermal resistance junction-to-case 5 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range -40 to 125 c p tot maximum power dissipation at t a = 25 c 2.25 w
l6728d electrical specifications doc id 16498 rev 1 7/33 4 electrical specifications 4.1 absolute maximum ratings table 4. absolute maximum ratings 4.2 electrical characteristics v cc = 5 v to 12 v; t j = 0 to 70 c unless otherwise specified symbol parameter value unit vcc to gnd -0.3 to 15 v v boot, v ugate to phase to gnd to gnd; t < 200 ns 15 33 45 v v phase to gnd to gnd; t < 200 ns -5 to 18 -8 to 30 v v lgate to gnd -0.3 to vcc+0.3 v fb, comp, vsen to gnd -0.3 to 3.6 v pgood to gnd -0.3 to vcc+0.3 v table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit supply current and power-on i cc vcc supply current ugate and lgate = open 6 ma i boot boot supply current ugate = open; phase to gnd 0.7 ma uvlo vcc turn-on vcc rising 4.1 v hysteresis 0.2 v oscillator f sw main oscillator accuracy 270 300 330 khz v osc pwm ramp amplitude 1.4 v d max maximum duty cycle 80 % reference and error amplifier output voltage accuracy -0.8 - 0.8 % a 0 dc gain (1) 120 db gbwp gain-bandwidth product (1) 15 mhz sr slew-rate (1) 8v/ s dis disable threshold comp falling 0.70 0.85 v
electrical specifications l6728d 8/33 doc id 16498 rev 1 gate drivers i ugate hs source current boot - phase = 5 v 1.5 a r ugate hs sink resistance boot - phase = 5 v 1.1 i lgate ls source current vcc = 5 v 1.5 a r lgate ls sink resistance vcc = 5 v 0.65 overcurrent protection i ocset ocset current source sourced from lgate pin, during oc setting phase. 91011 a v oc_sw oc switch-over threshold v lgate/oc rising 600 mv over and undervoltage protections ovp ovp threshold vsen rising 0.970 1.000 1.030 v un-latch, vsen fall ing 0.35 0.40 0.45 v uvp uvp threshold vsen falling 0.570 0.600 0.630 v vsen vsen bias current sourced from vsen 100 na pgood pgood upper threshold vsen rising 0.860 0.890 0.920 v lower threshold vsen falling 0.680 0.710 0.740 v v pgoodl pgood voltage low i pgood = -4 ma 0.4 v 1. guaranteed by design, not subject to test. table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
l6728d device description doc id 16498 rev 1 9/33 5 device description the l6728d is a single-phase pwm controller with embedded high-current drivers which provides complete control logic and protection features for easy implementation of a general dc-dc step-down converter. designed to drive n-channel mosfets in a synchronous buck topology, this 10-pin device provides a high level of integration to allow a reduction in cost and size of power supply solutions, while also providing real-time pgood in a compact dfn10 3x3 mm package. the l6728d is designed to operate from a 5 v or 12 v supply. the output voltage can be precisely regulated to as low as 0.8 v with 0.8% accuracy over line and temperature variations. the switching frequency is internally set to 300 khz. this device provides a simple control loop with a voltage-mode error amplifier. the error amplifier features a 15 mhz gain-bandwidth product and 8 v/s slew rate, allowing high regulator bandwidth for fast transient response. to prevent load damage, the l6728d provides protection against overcurrent, overvoltage, undervoltage and feedback disconnection. the overcurrent trip threshold is programmable using a resistor connected from lgate to gnd. output current is monitored across the low- side mosfet r ds(on) , eliminating the need for expensive and space-consuming sense resistors. output voltage is moni tored through the dedicated vsen pin. the l6728d implements soft-start by increasing the internal reference in closed-loop regulation. the low side-less feature allows the device to perform soft-start over a pre- biased output, avoiding high current return through the output inductor and dangerous negative spike at the load side. the l6728d is available in a compact dfn10 3x3 mm package with exposed pad.
driver section l6728d 10/33 doc id 16498 rev 1 6 driver section the integrated high-current drivers permit the use of different types of power mosfets (also multiple mosfets to reduce the equivalent r ds(on) ), maintaining fast switching transition. the driver for the high-side mosfet uses the boot pin for supply and the phase pin for return. the driver for low-side mosfet uses the vcc pin for supply and the gnd pin for return. the controller embodies an anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time, maintaining good efficiency while eliminating the need for a schottky diode: to check the high-side mosf et turn-off, the phase pin is sensed. when the voltage at the phase pin drops, the low-side mo sfet gate drive is suddenly applied to check the low-side mosfet turn-off, the lgate pin is sensed. when the voltage at lgate has fallen, the high-side mosfet gate drive is suddenly applied if the current flowing in the in ductor is negative, voltage on the phase pin will never drop. to allow the low-side mosfet to turn on ev en in this case, a wa tchdog controller is enabled. if the source of the high-side mosfet does not drop, the low side mosfet is switched on, thereby allowing the negative current of the inductor to recirculate. this mechanism allows the system to regulate even if the current is negative. power conversion input is flexible: 5 v, 12 v bus or any bus that allows the conversion (see maximum duty cycle limitations) to be chosen freely. 6.1 power dissipation the l6728d embeds high current mosfet drivers for both high side and low side mosfets. it is therefore important to consider the power that the device is going to dissipate in driving them, in order to avoid overcoming the maximum junction operating temperature. two main factors contribute to device power dissipation: bias power and driver power. device bias power (p dc ) depends on the static consumption of the device through the supply pins, and is quantifiable as follows (assuming hs and ls drivers with the same vcc of the device): driver power is the power needed by the driver to continuously switch on and off the external mosfets. it is a function of the switching frequency and total gate charge of the selected mosfets. it can be quantified considering that the total power p sw dissipated to switch the mosfets (easily ca lculable) is dissipated by three main factors: external gate resistance (when present), intrinsic mosfet resistance and intrinsic driver resistance. this last factor is the most important one to be determined to calculate the device power dissipation. the total power dissipated to switch the mosfets is: p dc v cc i cc i boot + () ? = p sw f sw q ghs v boot q gls v cc ? + ? () ? =
l6728d driver section doc id 16498 rev 1 11/33 external gate resistors help the device to dissipate the switching power since the same power p sw is shared between the internal driver impedance and the external resistor, resulting in a general cooling of the device.
soft-start l6728d 12/33 doc id 16498 rev 1 7 soft-start the l6728d implements a soft-start to smoothly charge the output filter, avoiding the high in-rush currents to be required from the input power supply. the device gradually increases the internal reference from 0 v to 0.8 v in 4.5 ms (typ.), in closed-loop regulation, linearly charging the output capacitors to the final regulation voltage. in the event of overcurrent triggering during soft-start, the overcurrent logic overrides the soft-start sequence and shuts down the pwm logic and both the high side and low side gates. this condition is latc hed. cycle the vcc to recover. the device begins the soft-start phase only when the vcc power supply is above the uvlo threshold and the overcurrent threshold setting phase has been completed. 7.1 low-side-less startup (lsless) in order to avoid any kind of negative undershoot and dangerous return from the load during startup, the l6728d performs a special sequence in enabling the ls driver to switch: during the soft-start phase, the ls driver is disabled (ls = off) until the hs starts to switch. this prevents the dangerous negative spike on the output voltage which can happen if starting over a pre-biased output. if the output voltage is pre-biased to a voltage higher than the final one, the hs would never start to switch. in this case, at the end of soft-start time, ls is enabled and discharges the output to the final regulation value. this particular feature of the device masks the ls turn-on only from the control loop point of view: protection features bypass this turning on of the ls mosfet if needed. figure 4. lsless startup (left) vs. non-lsless startup (right)
l6728d overcurrent protection doc id 16498 rev 1 13/33 8 overcurrent protection the overcurrent function protects the converter from a shorted output or overload, by sensing the output current information across the low side mosfet drain-source on- resistance, r ds(on) . this method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. the low side r ds(on) current sense is impl emented by comparing th e voltage at the phase node when the ls mosfet is turned on with the programmed ocp threshold voltages, internally held. if the monitored voltage is higher than these thresholds, an overcurrent event is detected. for maximum safety and load protection, the l6728d implements a dual-level overcurrent protection system: 1 st level threshold : this is the user externally-set threshold. if the monitored voltage on phase exceeds this threshold, a 1 st level overcurrent is detected. if four 1 st level oc events are detected in four consecutive switching cycles, overcurrent protection is triggered. 2 nd level threshold : this is an internal threshold whose value is equal to the 1 st level threshold multiplied by a factor 1.5. if the monitored voltage on phase exceeds this threshold, overcurrent protection is triggered immediately. when overcurrent protection is triggered, the device turns off both the ls and hs mosfets in a latched condition. to recover from an overcurrent protection-triggered condition, the vcc power supply must be cycled.
overcurrent protection l6728d 14/33 doc id 16498 rev 1 8.1 overcurrent threshold setting the l6728d allows easy programming of a 1 st level overcurrent threshold ranging from 50 mv to 550 mv, simply by adding a resistor (r ocset ) between lgate and gnd. the 2 nd level threshold is automat ically set accordingly. during a short period of time (about 5 ms) following vcc rising over uvlo threshold, an internal 10 a current (i ocset ) is sourced from the lgate pin, determining a voltage drop across r ocset . this voltage drop is sampled and inte rnally held by the device as a 1 st level overcurrent threshold. the oc setting procedure?s overall time period is about 5 ms. connecting an r ocset resistor between lgate and gnd, the programmed 1 st level threshold is: the programmed 2 nd level threshold is: r ocset values range from 5 k to 55 k . in case r ocset is not connected, the device sets the ocp thresholds to the maximum values: an internal safety clamp on lgate is triggered as soon as the lgate voltage reaches 600 mv, setting the maximum threshold and suddenly ending the oc setting phase. i octh1 i ocset r ocset ? r dson --------------- -------------- -------------- - = i octh2 1.5 i ocset r ocset ? r dson --------------- --------------- ------------- - ? =
l6728d output voltage setting and protections doc id 16498 rev 1 15/33 9 output voltage setting and protections the l6728d is capable of precisely regulating an output voltage as low as 0.8 v. in fact, the device is equipped with a fixed 0.8 v internal reference that guarantees the output regulated voltage remains within a 0.8% tolerance over line and temperature variations (excluding output resistor divider tolerance, when present). output voltages higher than 0.8 v can be easily achieved by adding a resistor r os between the fb pin and ground. referring to figure 1 , the steady-state dc output voltage is: where v ref is 0.8 v. the l6728d monitors the voltage at the vsen pin and compares it to the internal reference voltage in order to provide undervoltage and overvoltage protection as well as a pgood signal. depending on the level of vsen, differ ent actions are perfor med by the controller: pgood: if the voltage monitored through vsen goes outside the pgood window limits, the device de-asserts the pgood signal while still continuing to switch and regulate. pgood is asserted at the end of the soft-start phase. undervoltage protection: if the voltage at vsen pin dr ops below the uv threshold, the device turns off both the hs and ls mo sfets, latching the condition. cycle the vcc to recover. overvoltage protection: if the voltage at vsen pin rises over ov threshold (1 v typ), overvoltage protection turns off the hs mosfet and turns on the ls mosfet. the ls mosfet is turned off as soon as vsen goes below vref/2 (0.4 v). the condition is latched. cycle the vcc to recover. note that even if the device is latched, the device still controls the ls mo sfet and can switch it on when ever vsen rises above the ov threshold. feedback disconnection protection: in order to provide load protection even if the vsen pin is not connected, a 10 0 na bias current is always sourced from th is pin. if vsen pin is not connected, this current permanently pulls it up, causing the device to detect an ov. thus, ls is latched on, preventing the output voltage from rising out of control. v out v ref 1 r fb r os ---------- - + ?? ?? ? =
application details l6728d 16/33 doc id 16498 rev 1 10 application details 10.1 compensation network the control loop shown in figure 5 is a voltage mode control loop. the output voltage is regulated to the internal reference (when present, the offset resistor between the fb node and gnd can be neglected in control loop calculation). the error amplifier out put is compared to the oscillator sawtooth waveform to provide the pwm signal to the driver section. the pwm signal is then transferred to the switching node with v in amplitude. this waveform is filtered by the output filter. the converter transfer function is the small signal transfer function between the output of the ea and v out . this function has a double pole at frequency f lc depending on the l-c out resonance and a zero at f esr depending on the output capacitor esr. the dc gain of the modulator is simply the input voltage v in divided by the peak-to- peak oscilla tor voltage v osc . figure 5. pwm control loop the compensation network closes the loop, joining the v out and ea output with transfer function ideally equal to -z f / z fb . the compensation goal is to close the control loop while assuring high dc regulation accuracy, good dynamic performance and stabilit y. to achieve this, the overall loop needs high dc gain, high bandwidth and good phase margin. high dc gain is achieved by giving an integrator shape to the compensation network transfer function. the loop bandwidth (f 0db ) can be fixed by choosing the correct r f /r fb ratio. however, for stability, it should not exceed f sw /2 . to achieve a good phase margin, the control loop gain must cross the 0 db axis with -20 db/decade slope. as an example, figure 6 shows an asymptotic bode plot of a type iii compensation. l r c out esr r f c f c p r fb c s osc v in v osc + + _ _ v out v ref z f z fb pwm comparator error amplifier r s
l6728d application details doc id 16498 rev 1 17/33 figure 6. example of type iii compensation open loop converter singularities: a) b) compensation network singularities frequencies: a) b) c) d) to place the poles and zeroes of the compensation network, the following suggestions can be followed: a) set the gain r f /r fb in order to obtain the desired closed loop regulator bandwidth according to the approximated formula (suggested values for r fb are in the range of a few k ): gain [db] log (freq) 0db open loop ea gain closed loop gain compensation gain open loop converter gain f lc f esr f z1 f z2 f p1 f p2 20log (r f /r fb ) 20log (v in / v osc ) f 0db f lc 1 2 lc out ? ---------------------------------- = f esr 1 2 c out esr ?? ------------------------------------------- - = f z1 1 2 r f c f ?? ------------------------------ = f z2 1 2 r fb r s + () c s ?? ---------------------------------------------------- - = f p1 1 2 r f c f c p ? c f c p + --------------------- ?? ?? ?? -------------------------------------------------- = f p2 1 2 r s c s ?? ------------------------------ - = r f r fb ---------- f 0db f lc ------------ v osc v in ------------------ - ? =
application details l6728d 18/33 doc id 16498 rev 1 b) place f z1 below f lc (typically 0.5*f lc ): c) place f p1 at f esr : d) place f z2 at f lc and f p2 at half of the switching frequency: e) check that the compensation network gain is lower than open loop ea gain before f 0db f) check the phase margin obtained (it should be greater than 45) and repeat if necessary. 10.2 layout guidelines the l6728d provides control functions and high current integrated drivers to implement high-current step-down dc-dc converters. in this type of application, a good layout is very important. the first priority when placing components for these applications must be reserved for the power section, minimizing the length of each connection and loop as much as possible. to minimize noise and voltage spikes (emi and losses) power connections (highlighted in figure 7 ) must be a part of a power plane and in any case constructed with wide and thick copper traces. the loop must be minimized. the critical components, i.e. the power mosfets, must be close to each other. the use of multi-layer printed circuit boards is recommended. the input capacitance (c in ), or at least a portion of the total capacitance needed, must be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. low esr and esl capacitors are preferred. mlcc are suggested to be connected near the hs drain. use the appropriate number of vias when power traces have to move between different planes on the pcb in order to reduce both parasitic resistance and inductance. moreover, reproducing the same high-current trace on more than one pcb layer reduces the parasitic resistance associated with that connection. connect output bulk capacitors (c out ) as near as possible to the load, minimizing parasitic inductance and resistance associated with the copper trace, and also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitor bank. c f 1 r f f lc ?? ----------------------------- = c p c f 2 r f c f f esr 1 ? ??? ---------------------------------------------------------- = r s r fb f sw 2f ? lc ----------------- - 1 ? --------------------------- = c s 1 r s f sw ?? ------------------------------- =
l6728d application details doc id 16498 rev 1 19/33 figure 7. power connections (heavy lines) gate traces and phase traces must be sized according to the driver rms current delivered to the power mosfet. the device robustness allows the management of applications with the power section far from the controller without compromising performance. in any case, when possible it is recomm ended to minimize the distance between the controller and power section. small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. locate bypass capacitor (vcc and bootstrap capacitor) and feedback compensat ion components as close to the device as practical. for overcurrent programmability, place r ocset close to the device and avoid leakage current paths on the lgate / oc pin, si nce internal current source is only 10 a. systems that do not use a schottky diode in parallel to the low-side mosfet might show big negative spikes on the phase pin. this spike must be limited within the absolute maximum ratings (for example, adding a gate resistor in series to the hs mosfet gate), as well as the positive spike, but has an additi onal consequence: it causes the bootstrap capacitor to be over-charged. this extra charge can cause, in the worst-case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the absolute maximum ratings, also causing device failures. it is then suggested in this cases to limit this extra charge by adding a small resistor in series to the bootstrap diode. figure 8. driver turn-on and turn-off paths l c in v in ugate phase lgate gnd load l6728a c out l6728d r gate r int c gd c gs c ds vcc ls driver ls mosfet gnd lgate r gate r int c gd c gs c ds boot hs driver hs mosfet phase ugate
application information l6728d 20/33 doc id 16498 rev 1 11 application information 11.1 inductor design the inductance value is defined by a compromise between the dynamic response time, the efficiency, the cost and the size. the inductor has to be calculated to maintain the ripple current ( i l ) between 20% and 30% of the maximum output current (typ). the inductance value can be calculated with the following equation: where f sw is the switching frequency, v in is the input voltage and v out is the output voltage. figure 9 shows the ripple current vs. the output voltage for different values of the inductor, with v in = 5 v and v in = 12 v. increasing the value of the inductance reduces the current ripple but, at the same time, increases the converter response time to a dynamic load change. the response time is the time required by the inductor to change its curren t from initial to final va lue. until the inductor has finished its charging time, the output current is supplied by the output capacitors. minimizing the response time can minimi ze the output capacitance required. if the compensation network is well-designed, during a load variation the device is able to set a duty cycle value very different (0% or 80%) from a steady-state one. when this condition is reached, the response time is limited by the time required to change the inductor current. figure 9. inductor current ripple vs output voltage l v in v out ? f sw i l ? ----------------------------- - v out v in -------------- ? =
l6728d application information doc id 16498 rev 1 21/33 11.2 output capacitor(s) the output capacitors are basic components to define the ripple voltage across the output and for the fast transient response of the power supply. they depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. during steady-state conditions, the output voltage ripple is influenced by both the esr and capacitive value of the output capacitors as follow: where i l is the inductor current ripple. in particular, the expression that defines v out_c takes into consideration the output capacitor charge and discharge as a consequence of the inductor current ripple. during a load variation, the output capacitor supplies the current to the load or absorbs the current stored into the inductor until the converter reacts. in fact, even if the controller immediately recognizes the load transient and sets the duty cycle at 80% or 0%, the current slope is limited by the inductor value. the output voltage has a drop that, in this case also, depends on the esr and capacitive charge/discharge as follows: where v l is the voltage applied to the inductor during the transient response ( for the load appliance or v out for the load removal). mlcc capacitors have typically low esr to minimize the ripple but also have low capacitances that do not minimize the voltage deviation during dynamic load variations. on the contrary, electrolytic capacitors have big capacitances to minimize voltage deviation during load transients, while they do not show the same esr values of the mlcc resulting then in higher ripple voltages. for these reasons, a mix between electrolytic and mlcc capacitor is suggested to minimize ripple and reduce voltage deviation in dynamic mode. 11.3 input capacitors the input capacitor bank is designed consid ering mainly the inpu t rms current, which depends on the output deliverable current (i out ) and the duty cycle (d) for regulation as follows: the equation reaches its maximum value, i out /2, with d = 0.5. the losses depend on the input capacitor?s esr and, in the worst case, are: v out_esr i l esr ? = v out_c i l 1 8c out f sw ?? -------------------------------------- - ? = v out_esr i out esr ? = v out_c i out l i out ? 2c out v l ?? ------------------------------------- - ? = d max v in v out ? ? i rms i out d1d ? () ? ? = pesri out 2 ? () 2 ? =
20 a demonstration board l6728d 22/33 doc id 16498 rev 1 12 20 a demonstration board the l6728d demonstration board is constructed us ing a four-layer pcb, and is designed as a step-down dc-dc converter. the board demonstrates the operation of the device in a general-purpose application. the input voltage can range from 5 v to 12 v buses and the output voltage is fixed at 1.25 v. the application can deliver an output current up to 30 a. the switching frequency is 300 khz. figure 10. 20 a demonstration board (left) and component placement (right) figure 11. 20 a demonstration board top (left) and bottom (right) layers figure 12. 20 a demonstration board inner layers
l6728d 20 a demonstration board doc id 16498 rev 1 23/33 figure 13. 20 a demonstration board schematic
20 a demonstration board l6728d 24/33 doc id 16498 rev 1 table 6. 20 a demonstration board - bill of material qty reference description package capacitors 2c1, c2 electrolytic capacitor 1800 f 16 v nippon chemi-con kzj or kzg radial 10 x 25 mm 1 c10 mlcc, 100 nf, 16v, x7r smd0603 3 c11 to c13 mlcc, 4.7 f, 1 6 v, x 5 r murata grm31cr61c475ma01 smd1206 2 c14, c38 mlcc, 1 f, 16v, x7r smd0805 2c15, c19 mlcc, 10 f, 6.3 v, x7r murata grm31cr70j106ka01l smd1206 2c18, c20 electrolytic capacitor 2200 f 6.3 v nippon chemi-con kzj or kzg radial 10 x 20 mm 1 c23 mlcc, 6.8 nf, x7r smd0603 1 c24 mlcc, 33 nf, x7r 1 c35 mlcc, 68 pf, x7r resistors 4 r1, r2, r20, r17 resistor, 3r3, 1/16w, 1% smd0603 4 r3, r5, r11, r16 resistor, 0r, 1/8w, 1% smd0805 1 r4 resistor, 1r8, 1/8w, 1% 2 r6, r9 resistor, 2k2, 1/16w, 1% smd0603 2 r8, r13 resistor, 3k9, 1/16w, 1% 1 r7 resistor, 18k, 1/16w, 1% 1 r19 resistor, 22k, 1/16w, 1% 1 r18 resistor, 20k, 1/16w, 1% inductor 1l1 inductor, 1.25 h, t60-18, 6 turns easymagnet ap106019006p-1r1m na active components 1 d1 diode, 1n4148 or bat54 sot23 1 q5 std70n02l dpack 1 q7 std95nh02lt4 1 u1 controller, l6728d dfn10, 3x3 mm
l6728d 20 a demonstration board doc id 16498 rev 1 25/33 12.1 board description 12.1.1 power input (vin) this is the input voltage for the power conversion. the high-side drain is connected to this input. this voltage can range from 1.5 v to 12 v bus. if the voltage is between 4.5 v and 12 v it can also supply the device (through the vcc pin) and in this case the r16 (0 ) resistor must be present. 12.1.2 output (vout) the output voltage is fixed at 1.25 v but can be changed by replacing the resistors r8 (sense partition lower resistor) and r13 (fee dback partition lower resistor). r18 allows adjustment of the ocp threshold. 12.1.3 signal input (vcc) when using the input voltage vin to supply the controller, no power is required at this input. however the controller can be supplied separately from the power stage through the vcc input (4.5-12 v) and, in this case, the r16 (0 ) resistor must be unsoldered. 12.1.4 test points several test points are provided for easy access to all the important signals that characterize the device: ? comp: the output of the error amplifier ? fb: the inverting input of the error amplifier ? pgood: signaling regular functioning (active high) ? vgdhs: the bootstrap diode anode ? phase: phase node ? lgate: low-side gate pin of the device ? hgate: high-side gate pin of the device 12.1.5 board characterization figure 14. 20 a demonstration board efficiency
5 a demonstration board l6728d 26/33 doc id 16498 rev 1 13 5 a demonstration board the l6728d demonstration board is constructed using a two-layer pcb, and is designed as a step-down dc-dc converter. the board demonstrates the operation of the device in a general-purpose, low-current application. the input voltage can range from 5 v to 12 v buses and the output voltage is fixed at 1.25 v. the application can deliver an output current in excess of 5 a. the switching frequency is 300 khz. figure 15. 5 a demonstration board (left) and component placement (right) figure 16. 5 a demonstration board top (left) and bottom (right) layers
l6728d 5 a demonstration board doc id 16498 rev 1 27/33 figure 17. 5 a demonstration board schematic phase pin boot boot gnd fb comp phase out out out out out out out out out out out out out out out out ugate hsg1 lgate lgate vcc vcc_pin gnd lgate lgate lgate ugate phase pin comp vsen fb fb fb vcc_pin out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out lsg1 lsg1 lsg1 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc out out out out out out out out out out hsd vin_power vsen vsen 0 0 0 vin_power gndin_power 0 vcc gndcc 0 0 0 vout 0 gndout 0 0 0 0 0 0 0 & r p s h q v d w l r q 1 h w z r u n ! s o d f h q h d u w k h f r q w u r o o h u " ( o h f w u r o \ w l f f d s d f l w r u ! g x d o i r r w s u l q w " 7 d q w d o x p f d s d f l w r u v ! g x d o i r r w s u l q w " f h u d p l f f d s d f l w r u v ! g x d o i r r w s u l q w " f h u d p l f f d s d f l w r u v ! s o d f h q h d u + 6 p r v " ' x d o 0 r v i h w 6 7 6 ' 1 + / / /6 /8 r14 15 r14 15 comp comp 1 2 l2 2.2uh l2 2.2uh fb fb gnd gnd vout1 vout1 r4 1.8 r4 1.8 c30 330uf c30 330uf vsen vsen r13 3.9k r13 3.9k c23 6.8nf c23 6.8nf r3 0 r3 0 c36 6.8nf c36 6.8nf r8 3.9k r8 3.9k gndout1 gndout1 gndin1 gndin1 r6 2.2k r6 2.2k 4 3 5 q5a q5a r9 2.2k r9 2.2k c38 1uf c38 1uf r17 3.3 r17 3.3 c51 10uf c51 10uf vin1 vin1 r16 0 r16 0 phase phase c10 100nf c10 100nf pgood pgood c35 220pf c35 220pf c40 nc c40 nc 2 1 7 q5b q5b c14 1uf c14 1uf c29 nc c29 nc r18 10k r18 10k c18 nc c18 nc r7 4.7k r7 4.7k r5 0 r5 0 lgate lgate c24 68nf c24 68nf d1 bat54 d1 bat54 c12 10uf c12 10uf r1 3.3 r1 3.3 gnd 5 ugate 3 vcc 6 phase 2 boot 1 comp 7 fb 8 lgate 4 vsen 9 pgood 10 l6728d u1 l6728 u1 vcc vcc c39 22uf c39 22uf r2 3.3 r2 3.3 r19 22k r19 22k
5 a demonstration board l6728d 28/33 doc id 16498 rev 1 table 7. 5 a demonstration board - bill of material qty reference description package capacitors 2 c12, c51 mlcc, 10 f, 2 5 v, x 5 r murata grm31cr61e106ka12 smd1206 1 c10 mlcc, 100 nf, 16 v, x7r smd0603 2 c14, c38 mlcc, 1 f, 16 v, x7r smd0805 1c39 mlcc, 22 f, 6.3 v, x5r murata grm31cr60j226me19l smd1206 1c30 330 f, 6.3 v, 9 m sanyo 6tpf330m9l smd7343 2 c23, c36 mlcc, 6.8 nf, x7r smd0603 1 c24 mlcc, 68 nf, x7r 1 c35 mlcc, 220 pf, x7r resistors 3 r1, r2, r17 resistor, 3r3, 1/16 w, 1% smd0603 3 r3, r5, r16 resistor, 0r, 1/16 w, 1% smd0603 1 r4 resistor, 1r8, 1/8 w, 1% smd0805 1 r14 resistor, 15r, 1/16 w, 1% smd0603 2 r6, r9 resistor, 2k2, 1/16 w, 1% smd0603 2 r8, r13 resistor, 3k9, 1/16 w, 1% 1 r7 resistor, 4k7, 1/16 w, 1% 1 r19 resistor, 22k, 1/16 w, 1% 1 r18 resistor, 10k, 1/16 w, 1% inductor 1l1 inductor, 2.2 h, wurth 744324220lf na active components 1 d1 diode, bat54 sot23 1 q5 sts9d8nh3ll so8 1 u1 controller, l6728d dfn10, 3x3 mm
l6728d 5 a demonstration board doc id 16498 rev 1 29/33 13.1 board description 13.1.1 power input (vin) this is the input voltage for the power conversion. the high-side drain is connected to this input. this voltage can range from 1.5 v to 12 v bus. if the voltage is between 4.5 v and 12 v, it can also supply the device (through the vcc pin), and in this case the r16 (0 ) resistor must be present. 13.1.2 output (vout) the output voltage is fixed at 1.25 v, but can be changed by replacing resistors r8 (sense partition lower resistor) and r13 (feedback partition lower resistor). r18 allows the adjustment of the ocp threshold. 13.1.3 signal input (vcc) when using the input voltage vin to supply the controller, no power is required at this input. however, the controller can be supplied separately from the power stage through the vcc input (4.5-12 v) and, in this case, the r16 (0 ) resistor must be unsoldered. 13.1.4 test points several test points are provided for easy access to all the important signals that characterize the device: ? comp: the output of the error amplifier ? fb: the inverting input of the error amplifier ? pgood: signaling regular functioning (active high) ? vgdhs: the bootstrap diode anode ? phase: phase node ? lgate: low-side gate pin of the device ? hgate: high-side gate pin of the device
5 a demonstration board l6728d 30/33 doc id 16498 rev 1 13.1.5 board characterization figure 18. 5 a demonstration board efficiency
l6728d package mechanical data doc id 16498 rev 1 31/33 14 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 19. package dimensions table 8. dfn10 mechanical data dim. mm mils min. typ. max. min. typ. max. a 0.80 0.90 1.00 31.5 35.4 39.4 a1 0.02 0.05 0.8 2.0 a2 0.70 27.6 a3 0.20 7.9 b 0.18 0.23 0.30 7.1 9.1 11.8 d 3.00 118.1 d2 2.21 2.26 2.31 87.0 89.0 90.9 e 3.00 118.1 e2 1.49 1.64 1.74 58.7 64.6 68.5 e 0.50 19.7 l 0.3 0.4 0.5 11.8 15.7 19.7 m 0.75 29.5 m 0.25 9.8 m m
revision history l6728d 32/33 doc id 16498 rev 1 15 revision history table 9. document revision history date revision changes 03-feb-2010 1 initial release.
l6728d doc id 16498 rev 1 33/33 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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